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  • 22 December 2021 10:49

Weebit Nano receives first silicon integrated ReRAM demonstration chips

Weebit Nano Limited (ASX:WBT) has received from manufacturing the first silicon wafers that integrate its embedded Resistive Random-Access Memory (ReRAM) module inside complete subsystem demonstration (demo) chips.

Locally listed Weebit Nano Limited (ASX:WBT) a leading developer of next-generation memory technologies for the global semiconductor industry, has received from manufacturing the first silicon wafers that integrate its embedded Resistive Random-Access Memory (ReRAM) module inside complete subsystem demonstration (demo) chips.

These highly integrated chips will be used for testing and characterisation, as well as for demonstration to potential customers. Importantly, the demo chips will allow customers to run applications to test Weebit’s ReRAM technology ahead of potential commercial orders and volume production for their specific chips.

Weebit worked with its development partner CEA-Leti to successfully manufacture the demo wafers. The wafers will now be sliced into chips, packaged, and then tested, characterised and qualified. Chips based on this design will be used for the qualification process in SkyWater Technology’s US production fab. The transfer of Weebit’s embedded ReRAM technology to SkyWater Technology’s production fab is progressing on schedule.

Coby Hanoch, CEO of Weebit Nano, said, “We are proud to deliver another significant commercialisation milestone on-time. The demo chips integrating Weebit’s ReRAM module will support the adoption of our technology by potential customers looking to address the shortcomings of flash memory. We will now be able to provide customers with a fully functional ReRAM technology that can be readily integrated into their Systems-on-Chips [SoCs] to facilitate the design of new embedded products that are moving beyond flash.”

Weebit’s embedded ReRAM module includes a 128Kb ReRAM array, control logic, decoders, IOs (Input/Output communication elements) and error correcting code (ECC). It is designed with unique patent-pending analog and digital smart circuitry that significantly enhances the memory array’s technical parameters including speed, retention, and endurance. It is easily customisable and will provide a foundation for Weebit’s future ReRAM compiler.

In addition to Weebit’s ReRAM module, the demo chip includes a RISC-V microcontroller (MCU), system interfaces, SRAM and peripherals – altogether comprising a full sub-system for embedded applications.

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